Intel Senior EDA Software Engineer in San Jose, California

Job Description

As an experienced Software Engineer in the Quartus Implementation Tools team, you will be developing FPGA Placement, Routing and Physical Synthesis algorithms. We are looking for engineers with P&R expertise who have developed similar technologies for ASIC/FPGA. Responsibilities for this position require developing innovative software that can improve Quartus tool metrics such as timing Quality of Results (QoR) and routability of designs targeting Intel FPGAs. Responsibilities also include leading projects to improve tool runtime and memory footprint. Successful execution of these responsibilities would require deep understanding of electronic design automation (EDA) optimization algorithms, static timing analysis, interconnect modeling and other physical design concepts.


Minimum Qualifications: BS in Electrical Engineering, Computer Science, Computer Engineering, or related field AND 6 years of work experience developing:

  • Algorithms for EDA software

  • C++ Data structures, algorithms and optimization techniques

Preferred Qualifications: Master's or PhD in Electrical Engineering, Computer Science, Computer Engineering, or related field AND 8 years of work experience developing algorithms for EDA software in the areas of synthesis, physical synthesis, simulation, verification, or place and route.

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

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